?url_ver=Z39.88-2004&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Adc&rft.title=Self-Partial+and+Dynamic+Reconfiguration+Implementation+for+AES+using+FPGA&rft.creator=Alaoui+Ismaili%2C+Zine+El+Abidine&rft.creator=Moussa%2C+Ahmed+&rft.subject=Machine+Learning&rft.description=This+paper+addresses+efficient+hardware%2Fsoftware+implementation+approaches+for+the+AES+(Advanced+Encryption+Standard)+algorithm+and+describes+the+design+and+performance+testing+algorithm+for+embedded+system.+Also%2C+with+the+spread+of+reconfigurable+hardware+such+as+FPGAs+(Field+Programmable+Gate+Array)+embedded+cryptographic+hardware+became+cost-effective.+Nevertheless%2C+it+is+worthy+to+note+that+nowadays%2C+even+hardwired+cryptographic+algorithms+are+not+so+safe.+From+another+side%2C+the+self-reconfiguring+platform+is+reported+that+enables+an+FPGA+to+dynamically+reconfigure+itself+under+the+control+of+an+embedded+microprocessor.+Hardware+acceleration+significantly+increases+the+performance+of+embedded+systems+built+on+programmable+logic.+Allowing+a+FPGA-based+MicroBlaze+processor+to+self-select+the+coprocessors+uses+can+help+reduce+area+requirements+and+increase+a+system's+versatility.+The+architecture+proposed+in+this+paper+is+an+optimal+hardware+implementation+algorithm+and+takes+dynamic+partially+reconfigurable+of+FPGA.+This+implementation+is+good+solution+to+preserve+confidentiality+and+accessibility+to+the+information+in+the+numeric+communication.&rft.publisher=International+Journal+of+Computer+Science+Issues%2C+IJCSI&rft.date=2009-08&rft.type=Journal+(Paginated)&rft.type=PeerReviewed&rft.format=application%2Fpdf&rft.identifier=http%3A%2F%2Fcogprints.org%2F6694%2F1%2F2-33-40.pdf&rft.identifier=++Alaoui+Ismaili%2C+Zine+El+Abidine+and+Moussa%2C+Ahmed+++(2009)+Self-Partial+and+Dynamic+Reconfiguration+Implementation+for+AES+using+FPGA.++%5BJournal+(Paginated)%5D+++++&rft.relation=http%3A%2F%2Fcogprints.org%2F6694%2F