Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

Alaoui Ismaili, Zine El Abidine and Moussa, Ahmed (2009) Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA. [Journal (Paginated)]

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PDF (Z. E. A. Alaoui Ismaili and A. Moussa, "Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA", International Journal of Computer Science Issues, IJCSI, Volume 2, pp33-40, August 2009) - Submitted Version


This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication.

Item Type:Journal (Paginated)
Keywords:Cryptography; Embedded systems; Reconfigurable computing; Self-reconfiguration
Subjects:Computer Science > Machine Learning
ID Code:6694
Deposited By:International Journal of Computer Science Issues, IJCSI
Deposited On:14 Nov 2009 11:35
Last Modified:11 Mar 2011 08:57


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